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datasheet 5P1103 revision d 07/13/15 1 ?2015 integrated device technology, inc. programmable fanout buffer 5P1103 description the 5P1103 is a programmable fanout buffer intended for high performance consumer, networking, industrial, computing, and data-communications applications. configurations may be stored in on-chip one-time programmable (otp) memory or changed using i 2 c interface. the outputs are generated from a single reference clock. the input reference can be crystal, external single-ended or differential clock. the reference clock can come from one of the two redundant clock inputs and is selected by clksel pin. a glitchless manual switchov er function allows one of the redundant clocks to be selected during normal operation. see reference clock input section for details. two select pins allow up to 4 different configurations to be programmed and accessible using processor gpios or bootstrapping. the different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (us, japan, europe) or system production margin testing. the device may be configured to use one of two i 2 c addresses to allow multiple de vices to be used in a system. pin assignment features ? up to two high performance universal differential output pairs ? low rms additive phase jitter: 0.2ps ? four banks of internal non-volatile in-system programmable or factory programmable otp memory ? i 2 c serial programming interface ? one additional lvcmos output clock ? two universal output pairs: ? each configurable as one diff erential output pair or two lvcmos outputs ? i/o standards: ? single-ended i/os: 1.8v to 3.3v lvcmos ? differential i/os - lvpecl, lvds and hcsl ? input frequency ranges: ? lvcmos reference clock input (xin/ref) ? 1mhz to 200mhz ? lvds, lvpecl, hcsl diffe rential clock input (clkin, clkinb) ? 1mhz to 350mhz ? crystal frequency range: 8mhz to 40mhz ? individually selectable output voltage (1.8v, 2.5v, 3.3v) for each output pair ? redundant clock inputs with manual switchover ? programmable crystal load capacitance ? individual output enable/disable ? power-down mode ? 1.8v, 2.5v or 3.3v core v ddd , v dda ? available in 24-pin vfqfpn 4mm x 4mm package ? -40 to +85c industrial temperature operation 1 7 24-pin vfqfpn 19 13 xout xin/ref v dda clkin nc out2 clkinb clksel nc out2b v ddo 2 v dda sd/oe sel1/sda sel0/scl v dda nc nc out1b out1 v ddo 1 v ddd v ddo 0 out0_sel_i2cb epad 2 3 4 5 6 8 9 10 11 12 14 15 16 17 18 20 21 22 23 24
programmable fanout buffer 2 revision d 07/13/15 5P1103 datasheet functional block diagram applications ? ethernet switch/router ? pci express 1.0/2.0/3.0 ? broadcast video/audio timing ? multi-function printer ? processor and fpga clocking ? msan/dslam/pon ? fiber channel, san ? telecom line cards ? 1 gbe and 10 gbe xin/ref xout clkin clkinb clksel sd/oe sel1/sda sel0/scl v dda v ddd v ddo 0 out0_sel_i2cb v ddo 1 out1 out1b v ddo 2 out2 out2b v dda v dda otp and control logic
revision d 07/13/15 3 programmable fanout buffer 5P1103 datasheet table 1:pin descriptions number name description 1 clkin input pull-down differential clock input. weak 100kohms internal pull-down. 2 clkinb input pull-down complementary differential clock input. weak 100kohms internal pull-down. 3 xout input crystal oscillator interface output. 4 xin/ref input crystal oscillator interface input, or single-ended lvcmos clock input. ensure that the input voltage is 1.2v max. refer to the section ?overdriving the xin/ref interface?. 5 vdda power analog functions power supply pin. connect to 1.8v to 3.3v. vdda and v ddd should have the same voltage applied. 6 clksel input pull-down input clock select. selects the active input reference source, when in manual switchover mode. 0 = xin/ref, xout (default) 1 = clkin, clkinb clksel polarity can be changed by i2c programming as shown in table 4. 7 sd/oe input pull-down enables/disables the outputs (oe) or powers down the chip (sd). the sh bit controls the configuration of the sd/oe pin. the sh bit needs to be high for sd/oe pin to be configured as sd. the sp bit (0x02) controls the polarity of the signal to be either active high or low only when pin is configured as oe (default is active low.) weak internal pull down resistor. when configured as sd, device is shut down, differential outputs are driven high/low, and the single- ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs can be selected to be tri-stated or driven high/low, depending on the programming bits as shown in the sd/oe pin function truth table. 8 sel1/sda input pull-down configuration select pin, or i2c sda input as selected by out0_sel_i2cb. weak internal pull down resistor. 9 sel0/scl input pull-down configuration select pin, or i2c scl input as selected by out0_sel_i2cb. weak internal pull down resistor. 10 vdda power analog functions power supply pin. connect to 1.8v to 3.3v. vdda and v ddd should have the same voltage applied. 11 nc no connect. 12 nc no connect. 13 nc no connect. 14 nc no connect. 15 vdda power analog functions power supply pin. connect to 1.8v to 3.3v. vdda and v ddd should have the same voltage applied. 16 out2b output complementary output clock 2. please refer to the output drivers section for more details. 17 out2 output output clock 2. please refer to the output drivers section for more details. 18 vddo2 power output power supply. connect to 1.8 to 3.3v. sets output voltage levels for out2/out2b. 19 out1b output complementary output clock 1. please refer to the output drivers section for more details. 20 out1 output output clock 1. please refer to the output drivers section for more details. 21 vddo1 power output power supply. connect to 1.8 to 3.3v. sets output voltage levels for out1/out1b. 22 vddd power digital functions power supply pin. connect to 1.8 to 3.3v. vdda and vddb should have the same voltage applied. 23 vddo0 power power supply pin for out0_sel_i2cb. connect to 1.8 to 3.3v. sets output voltage levels for out0. 24 out0_selb_i2c input/output pull-down latched input/lvcmos output. at power up, the voltage at the pin out0_sel_i2cb is latched by the part and used to select the state of pins 8 and 9. if a weak pull up (10kohms) is placed on out0_sel_i2cb, pins 8 and 9 will be configured as hardware select pins, sel1 and sel0. if a weak pull down (10kohms) is placed on out0_sel_i2cb or it is left floating, pins 8 and 9 will act as the sda and scl pins of an i2c interface. after power up, the pin acts as a lvcmos reference output. epad vee power connect to ground pad. type
programmable fanout buffer 4 revision d 07/13/15 5P1103 datasheet configuration and input descriptions table 2: configuration table this table shows the sel1, sel0 settings to select the configuration stored in otp. four configurations can be stored in otp. these can be factory programmed or user programmed. at power up time, the sel0 and sel1 pins must be tied to either the vddd/vdda power supp ly so that they ramp with that supply or are tied low (thi s is the same as floating the pins). this will cause the regist er configuration to be loaded that is selected according to table 3 above. providing that out0_sel_i2cb was 1 at por and otp register 0:7=0, after the first 10ms of operation the levels of the selx pins can be changed, either to low or to the same level as vddd/vdda. the selx pins must be driven with a digital signal of < 300ns rise/fall time and only a single pin can be changed at a time. after a pin level change, the device must not be interrupted for at least 1ms so that the new values have time to load and take effect. if out0_sel_i2cb was 0 at por, alternate configurations can only be loaded via the i2c interface. table 3: input clock select input clock select. sele cts the active input reference source in manual switchover mode. 0 = xin/ref, xout (default) 1 = clkin, clkinb clksel polarity can be changed by i 2 c programming as shown in table 4. primsrc is bit 1 of register 0x13. out0_sel_i2cb @ por sel1 sel0 i 2 c access reg0:7 config 100no00 101no01 110no02 111no03 0 x x yes 1 i2c defaults 0xxyes00 primsrc clksel source 0 0 xin/ref 0 1 clkin, clkinb 1 0 clkin, clkinb 1 1 xin/ref
revision d 07/13/15 5 programmable fanout buffer 5P1103 datasheet reference clock input pins and selection the 5P1103 supports up to two clock inputs. one input supports a crystal between xin and xout. xin can also be driven from a single ended reference clock. xin can accept small amplitude signals like from tcxo or one channel of a differential clock. the second clock input (clkin, clkinb) is a fully differential input that only accepts a reference clock. the differential input accepts differential clocks from all the differential logic types and can also be driven from a single ended clock on one of the input pins. the clksel pin selects the in put clock between either xtal/ref or (clkin, clkinb). either clock input can be set as the primary clock. the primary clock designation is to establis h which is the main reference clock. the non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. the primsrc bit determines which clock input will be selected as primary clock. when primsrc bit is ?0?, xin/ref is selected as the pr imary clock, and when ?1?, (clkin, clkinb) as the primary clock. the two external reference clocks can be manually selected using the clksel pin. the sm bi ts must be set to ?0x? for manual switchover which is detailed in manual switchover mode section. crystal input (xin/ref) the crystal used should be a fundamental mode quartz crystal; overtone crystals should not be used. a crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. when the oscillator load capacitance matches the crystal load capacitance, the oscillation frequency will be accurate. when the oscillator load capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal and vice versa so for an accurate oscillation frequency you need to make sure to match the oscillator load capacitance with the crystal load capacitance. to set the oscillator load capacitance there are two tuning capacitors in the ic, one at xin and one at xout. they can be adjusted independently but commonly the same value is used for both capacitors. the value of each capacitor is composed of a fixed capacitance amount plus a variable capacitance amount set with the xtal[5:0] register. adjustment of the crystal tuning capacitors allows for maximum flexibility to accommod ate crystals from various manufacturers. the range of tuning capacitor values available are in accordance with the following table. xtal[5:0] tuning capacitor characteristics the capacitance at each crystal pin inside the chip starts at 9pf with setting 000000b and can be increased up to 25pf with setting 111111b. the step per bit is 0.5pf. you can write the following equation for this capacitance: ci = 9pf + 0.5pf xtal[5:0] the pcb where the ic and the crystal will be assembled adds some stray capacitance to each crystal pin and more capacitance can be added to each crystal pin with additional external capacitors. you can write the following equations for the total capacitance at each crystal pin: c xin = ci 1 + cs 1 + ce 1 c xout = ci 2 + cs 2 + ce 2 ci 1 and ci 2 are the internal, tunable capacitors. ci 1 and cs 2 are stray capacitances at each crystal pin and typical values are between 1pf and 3pf. ce 1 and ce 2 are additional external capacitors that can be added to increase the crystal load capacitance beyond the tuning range of the internal capacitors. however, increasing the load capacitance reduces th e oscillator gain so please consult the factory when adding ce 1 and/or ce 2 to avoid crystal startup issues. ce 1 and ce 2 can also be used to adjust for unpredictable stray capacitance in the pcb. the final load capacitance of the crystal: cl = c xin c xout / (c xin + c xout ) for most cases it is reco mmended to set the value for capacitors the same at each crystal pin: c xin = c xout = cx cl = cx / 2 the complete formula when the capacitance at both crystal pins is the same: cl = (9pf + 0.5pf xtal[5:0] + cs + ce) / 2 parameter bits step (pf) min (pf) max (pf) xtal 6 0.5 9 25 ?
programmable fanout buffer 6 revision d 07/13/15 5P1103 datasheet example 1 : the crystal load capacitance is specified as 8pf and the stray capacitance at each crystal pin is cs=1.5pf. assuming equal capacitance value at xin and xout, the equation is as follows: 8pf = (9pf + 0.5pf xtal[5:0] + 1.5pf) / 2 0.5pf xtal[5:0] = 5.5pf xtal[5:0] = 11 (decimal) example 2 : the crystal load capacitance is specified as 12pf and the stray capacitance cs is unknown. footprints for external capacitors ce are added and a worst case cs of 5pf is used. for now we use cs + ce = 5pf and the right value for ce can be determined later to make 5pf together with cs. 12pf = (9pf + 0.5pf xtal[5:0] + 5pf) / 2 xtal[5:0] = 20 (decimal) manual switchover mode when sm[1:0] is ?0 x?, the redundant inputs are in manual switchover mode. in this mode, clksel pin is used to switch between the primary and secondary clock sources. the primary and secondary clock source setting is determined by the primsrc bit. during the swit chover, no glitches will occur at the output of the device, al though there may be frequency and phase drift, depending on the exact phase and frequency relationship between the primary and secondary clocks. otp interface the 5P1103 can also store its configuration in an internal otp. the contents of the device's internal programming registers can be saved to the otp by setting burn_start (w114[3]) to high and can be loaded back to the internal programming registers by setting usr_rd_start(w114[0]) to high. to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to ?0?, followed by the appropriate command code. the save or restore instruction exec utes after the stop condition is issued by the ma ster, during which time the 5P1103 will not generate acknowledge bits. the 5P1103 will acknowledge the instructions after it has comple ted execution of them. during that time, the i 2 c bus should be interpreted as busy by all other users of the bus. on power-up of the 5P1103, an automatic restore is performed to load the otp contents into the internal programming registers. the 5p 1103 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. availability of prim ary and secondary i 2 c addresses to allow programming for multiple devices in a system. the i 2 c slave address can be changed from the default 0xd4 to 0xd0 by programming the i2c_addr bit d0. versaclock 5 programming guide provides detailed i 2 c programming guidelines and register map. sd/oe pin function the polarity of the sd/oe signal pin can be programmed to be either active high or low with the sp bit (w16[1]). when sp is ?0? (default), the pin becomes active low and when sp is ?1?, the pin becomes active high. the sd/oe pin can be configured as either to shutdown the pll or to enable/disable the outputs. the sh bit contro ls the configuration of the sd/oe pin the sh bit needs to be high for sd/oe pin to be configured as sd . when configured as sd, device is shut down, differential outputs are driven high/low, and the single-ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs are driven high/low. table 4: sd/oe pin fu nction truth table output skew rising edges of all outputs are automatically phase aligned. output drivers the out1 to out2 clock outputs are provided with register-controlled output drivers. by selecting the output drive type in the appropriate register, any of these outputs can support lvcmos, lvpecl, hcs l or lvds logic levels the operating voltage ranges of each output is determined by sd/oe input sp sh oen osn global shutdown outn sh bit sp bit osn bit oen bit sd/oe outn 0 0 0 x x tri-state 2 0 0 1 0 x output active 0 0 1 1 0 output active 0 0 1 1 1 output driven high low 0 1 0 x x tri-state 2 0 1 1 0 x output active 0 1 1 1 0 output driven high low 0 1 1 1 1 output active 1 0 0 x 0 tri-state 2 1 0 1 0 0 output active 1 0 1 1 0 output active 1 1 0 x 0 tri-state 2 1 1 1 0 0 output active 1 1 1 1 0 output driven high low 1x x x 1 output driven high low 1 note 1 : global shutdown note 2 : tri-state regardless of oen bits
revision d 07/13/15 7 programmable fanout buffer 5P1103 datasheet its independent output power pin (v ddo ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential hcsl, lvpecl operation, and 1. 8v, 2.5v, or 3.3v are supported for lvcmos and differential lvds operation. each output may be enabled or disabled by register bits. when disabled an output will be in a logic 0 state as determined by the programming bit table shown on page 6. lvcmos operation when a given output is configur ed to provide lvcmos levels, then both the outx and outx b outputs will toggle at the selected output frequency. all the previously described configuration and control apply equally to both outputs. frequency, phase alignment, voltage levels and enable / disable status apply to both the outx and outxb pins. the outx and outxb outputs can be selected to be phase-aligned with each other or inverted relative to one another by register programming bits. selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due to increased simultaneous switching noise within the device. device hardware configuration the 5P1103 supports an internal one-time programmable (otp) memory that can be pre-programmed at the factory with up to 4 complete device configuration. these configurations can be over-written using the serial interface once reset is complete . any configuration written via the programming interface needs to be re-written after any power cycle or reset. please contact idt if a specific factory-programmed configuration is desired. device start-up & reset behavior the 5P1103 has an internal power-up reset (por) circuit. the por circuit will remain active for a maximum of 10ms after device power-up. upon internal por circuit expi ring, the device will exit reset and begin self-configuration. the device will load inte rnal registers using the configuration stored in the internal one-time programmable (otp) memory. once the full confi guration has been loaded, the device will respond to accesses on the se rial port and will attempt to begin operation. power up ramp sequence vdda and vddd must ramp up together. vddo0~2 must ramp up before, or concurrently with, vdda and vddd. all power supply pins must be connected to a power rail even if the output is unused. all power supplies must ramp in a linear fashion and ramp monotonically. vddo0~2 vdda vddd
programmable fanout buffer 8 revision d 07/13/15 5P1103 datasheet i 2 c mode operation the device acts as a slave device on the i 2 c bus using one of the two i 2 c addresses (0xd0 or 0xd4) to allow multiple devices to be used in the sys tem. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at wh ich point, all data received in the block write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-down resistors ha ve a size of 100k ? typical. i 2 c slave read and write cycle sequencing current ? read s dev ? addr ? + ? r a data ? 0 a data ? 1 a a data ? n abar p sequential ? read s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n abar p reg ? start ? addr a sr dev ? addr ? + ? r a sequential ? write s dev ? addr ? + ? w a data ? 0 p a data ? 1 a a data ? n a from ? master ? to ? slave from ? slave ? to ? master reg ? start ? addr a s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge abar= ? none ? acknowledge p ? = ? stop
revision d 07/13/15 9 programmable fanout buffer 5P1103 datasheet table 5: i 2 c bus dc characteristics table 6: i 2 c bus ac characteristics note 1: a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 2: i2c inputs are 5v tolerant. symbol parameter conditions min typ max unit v ih input high level for sel1/sda pin and sel0/scl pin. 0.7xv ddd 5.5 2 v v il input low level for sel1/sda pin and sel0/scl pin. gnd-0.3 0.3xv ddd v v hys hysteresis of inputs 0.05xv ddd v i in input leakage current -1 30 a v ol output low voltage i ol = 3 ma 0.4 v symbol parameter min typ max unit f sclk serial clock frequency (scl) 10 400 khz t buf bus free time between stop and start 1.3 s t su:start setup time, start 0.6 s t hd:start hold time, start 0.6 s t su:data setup time, data input (sda) 100 ns t hd:data hold time, data input (sda) 1 0s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t f fall time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t high high time, clock (scl) 0.6 s t low low time, clock (scl) 1.3 s t su:stop setup time, stop 0.6 s
programmable fanout buffer 10 revision d 07/13/15 5P1103 datasheet table 7: absolute maximum ratings stresses above the ratings listed below can cause permanent da mage to the 5P1103. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating condition s for extended periods can af fect product reliability. electrical parameters ar e guaranteed only over th e recommended operating temperature range. table 8: recommended operation conditions note: v ddo 1 and v ddo 2 must be powered on either before or simultaneously with v ddd , v dda and v ddo 0. item rating supply voltage, v dda, v ddd, v ddo 3.465v inputs xin/ref clkin, clkinb other inputs 0v to 1.2v voltage swing 0v to 1.2v voltage swing single-ended -0.5v to v ddd outputs, v ddo (lvcmos) -0.5v to v ddo + 0.5v outputs, i o (sda) 10ma package thermal impedance, ? ja 42 ? c/w (0 mps) package thermal impedance, ? jc 41.8 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c esd human body model 2000v junction temperature 125c symbol parameter min typ max unit v ddox power supply voltage for supporting 1.8v outputs 1.71 1.8 1.89 v v ddox power supply voltage for support ing 2.5v outputs 2.375 2.5 2.625 v v ddox power supply voltage for support ing 3.3v outputs 3.135 3.3 3.465 v v ddd power supply voltage for core logic functions 1.71 3.465 v v dda analog power supply voltage. use filtered analog power supply. 1.71 3.465 v t a operating temperature, ambient -40 +85 c c load_out maximum load capacitance (3.3v lvcmos only) 15 pf f in external reference crystal 8 40 mhz external reference clock clkin, clkinb 1 350 t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 5 ms
revision d 07/13/15 11 programmable fanout buffer 5P1103 datasheet table 9: input capacitance, lvcmos outp ut impedance, and internal pull-down resistance (t a = +25 c) table 10: crystal characteristics note: typical crystal used is idt 603-25-150 or fox 603-25-150 . for different reference crystal options please go to www.foxonline.com . table 11: dc electrical characteristics 1. single cmos driver active. 2. measured into a 5? 50 ohm trace with 2 pf load. 3. iddcore = idda + iddd, no loads. symbol parameter min typ max unit cin input capacitance (sd/oe, sel1/sda, sel0/scl) 37pf pull-down resistor 100 300 k ? rout lvcmos output driver impedance (vddo = 1.8v, 2.5v, 3.3v) 17 ? xin/ref programmable capacitance at xin/ref 925pf xo ut programmable capacitance at xout 925pf parameter test conditions minimum typical maximum units mode of oscillation frequency 82540mhz equivalent series resistance (esr) 10 100 ? shunt capacitance 7pf load capacitance (cl) @ <=25 mhz 6 8 12 pf load capacitance (cl) >25m to 40m 6 8 pf maximum crystal drive level 100 w fundamental symbol parameter test conditions min typ max unit iddcore 3 core supply current 100 mhz on all outputs, 25 mhz refclk 45ma lvpecl, 350 mhz, 3.3v vddox 35 37 ma lvpecl, 350 mhz, 2.5v vddox 33 35 ma lvds, 350 mhz, 3.3v vddox 8 9 ma lvds, 350 mhz, 2.5v vddox 7 8 ma lvds, 350 mhz, 1.8v vddox 6 7 ma hcsl, 250 mhz, 3.3v vddox, 2 pf load 22 23 ma hcsl, 250 mhz, 2.5v vddox, 2 pf load 20 22 ma lvcmos, 50 mhz, 3.3v, vddox 1,2 56ma lvcmos, 50 mhz, 2.5v, vddox 1,2 45ma lvcmos, 50 mhz, 1.8v, vddox 1,2 34ma lvcmos, 200 mhz, 3.3v vddox 1 17 18 ma lvcmos, 200 mhz, 2.5v vddox 1,2 12 13 ma lvcmos, 200 mhz, 1.8v vddox 1,2 910ma iddpd power down current sd asserted, i2c programming 5 6 ma iddox output buffer supply current
programmable fanout buffer 12 revision d 07/13/15 5P1103 datasheet table 12: electrical charact eristics ? differential clock input parameters 1,2 (supply voltage v dda , v ddd , v ddo 0 = 3.3v 5%, 2.5v 5%, 1.8v 5%, ta = -40c to +85c) 1. guaranteed by design and characterization, not 100% tested in production. 2. slew rate measured through 75mv window centered around differential zero. table 13: dc electrical charact eristics for 3.3v lvcmos (v ddo = 3.3v5%, ta = -40c to +85c) 1 1. see ?recommended operating conditions? table. symbol parameter test conditions min typ max unit v ih input high voltage?clkin, cl kinb single-ended input 0.55 1.7 v v il input low voltage?clkin, clkinb single-ended input gnd - 0.3 0.4 v v swing input amplitude - clkin, clkinb peak to peak value, single-ended 200 1200 mv dv/dt input slew rate - clkin, clki nb measured differentially 0.4 8 v/ns i il input leakage low current v in = gnd -5 5 a i ih input leakage high current v in = 1.7v 20 a d tin input duty cycle measurement from differential waveform 45 55 % symbol parameter test conditions min typ max unit voh output high voltage ioh = -15ma 2.4 vddo v vol output low voltage iol = 15ma 0.4 v iozdd output leakage current (out1~4) tri-state outputs, vddo = 3.465v 5a iozdd output leakage current (out0) tri-state outputs, vddo = 3.465v 30 a vih input high voltage single-ended inputs - clksel, sd/oe 0.7xvddd vddd + 0.3 v vil input low voltage single-ended inputs - clksel, sd/oe gnd - 0.3 0.3xvddd v vih input high voltage single-ended input out0_sel_i2cb 2 vddo0 + 0.3 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v vih input high voltage single-ended input - xin/ref 0.8 1.2 v vil input low voltage single-ended input - xin/ref gnd - 0.3 0.4 v t r /t f input rise/fall time clksel, sd/oe, sel1/sda, sel0/scl 300 ns
revision d 07/13/15 13 programmable fanout buffer 5P1103 datasheet table 14: dc electrical char acteristics for 2.5v lvcmos (v ddo = 2.5v5%, ta = -40c to +85c) table 15: dc electrical char acteristics for 1.8v lvcmos (v ddo = 1.8v5%, ta = -40c to +85c) symbol parameter test conditions min typ max unit voh output high voltage ioh = -12ma 0.7xvddo vddd + 0.3 v vol output low voltage iol = 12ma 0.4 v iozdd output leakage current tri-state outputs, vddo = 2.625v 5a voh output high voltage ioh = -12ma, out0 0.6 xvddo vddd + 0.3 v vol output low voltage iol = 12ma, out0 0.4 v iozdd output leakage current tri-state outputs, vddo = 2.625v, out0 30 a vih input high voltage single-ended inputs - clksel, sd/oe 0.7xvddd vddd + 0.3 v vil input low voltage single-ended inputs - clksel, sd/oe gnd - 0.3 0.3xvddd v vih input high voltage single-ended input out0_sel_i2cb 1.7 vddo0 + 0.3 5 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v vih input high voltage single-ended input - xin/ref 0.8 1.2 v vil input low voltage single-ended input - xin/ref gnd - 0.3 0.4 v t r /t f input rise/fall time clksel, sd/oe, sel1/sda, sel0/scl 300 ns symbol parameter test conditions min typ max unit voh output high voltage ioh = -8ma 0.7 xvddo vddo v vol output low voltage iol = 8ma 0.25 x vddo v iozdd output leakage current tri-state outputs, vddo = 3.465v 5a voh output high voltage ioh = -8ma, out0 0.6 xvddo vddo v vol output low voltage iol = 8ma, out0 0.25 x vddo v iozdd output leakage current tri-state outputs, vddo = 3.465v, out0 30 a vih input high voltage single-ended inputs - clksel, sd/oe 0.7 * vddd vddd + 0.3 v vil input low voltage single-ended inputs - clksel, sd/oe gnd - 0.3 0.3 * vddd v vih input high voltage single-ended input out0_sel_i2cb 0.65 * vddo0 vddd0 + 0.3 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v vih input high voltage single-ended input - xin/ref 0.8 1.2 v vil input low voltage single-ended input - xin/ref gnd - 0.3 0.4 v t r /t f input rise/fall time clksel, sd/oe, sel1/sda, sel0/scl 300 ns
programmable fanout buffer 14 revision d 07/13/15 5P1103 datasheet table 16: dc electrical characteristics for lvds (v ddo = 3.3v+ 5% or 2.5v+ 5%, ta = -40c to +85c) table 17: dc electrical ch aracteristics for lvds (v ddo = 1.8v+ 5%, ta = -40c to +85c) table 18: dc electrical ch aracteristics for lvpecl (v ddo = 3.3v+ 5% or 2.5v+ 5%, ta = -40c to +85c) table 19: electrical character istics ? dif 0.7v low power hcsl differential outputs (v ddo = 3.3v5%, 2.5v5%, ta = -40c to +85c) 1. guaranteed by design and characterization. not 100% tested in production 2. measured from differential waveform. 3. slew rate is measured through the v swing voltage range centered around differential 0v. this results in a +/-150mv window around differential 0v. 4. v cross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 5. the total variation of all v cross measurements in any particular system. note that this is a subset of v cross min/max (v cross absolute) allowed. the intent is to limit v cross induced modulation by setting ? v cross to be smaller than v cross absolute. 6. measured from single-ended waveform. 7. measured with scope averaging off, using statistics function. variation is difference between min. and max. symbol parameter min typ max unit v ot (+) differential output voltage for the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 1.125 1.25 1.375 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v ddo 924ma i osd differential outputs short circuit current, v out + = v out -612ma symbol parameter min typ max unit v ot (+) differential output voltage for the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 0.8 0.875 0.95 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v ddo 924ma i osd differential outputs short circuit current, v out + = v out -612ma symbol parameter min typ max unit v oh output voltage high, terminated through 50 ? tied to v dd - 2 v v ddo - 1.19 v ddo - 0.69 v v ol output voltage low, terminated through 50 ? tied to v dd - 2 v v ddo - 1.94 v ddo - 1.4 v v swing peak-to-peak output voltage swing 0.55 0.993 v symbol parameter conditions min typ max units notes dv/dt slew rate scope averaging on 1 4 v/ns 1,2,3 v high voltage high statistical measurement on single-ended signal using oscilloscope math function (scope averaging on) 660 850 mv 1,6,7 v low voltage low -150 150 mv 1,6 v max maximum voltage measurement on single-ended signal using absolute value (scope averaging off) 1150 mv 1 v min minimum voltage -300 mv 1 v swing voltage swing scope averaging off 300 mv 1,2,6 v cross crossing voltage value scope averaging off 250 550 mv 1,4,6 ? v cross crossing voltage variation scope averaging off 140 mv 1,5
revision d 07/13/15 15 programmable fanout buffer 5P1103 datasheet table 20: ac timing el ectrical characteristics (v ddo = 3.3v+5% or 2.5v+5% or 1.8v 5%, ta = -40c to +85c) (spread spectrum generation = off) symbol parameter test conditions min. typ. max. units input frequency limit (xin) 840mhz input frequency limit (ref) 1200mhz input frequency limit (clkin, clkinb) 1350mhz single ended clock output limit (lvcmos) 1200 differential cock output limit (lvpecl/ lvds/hcsl) 1350 t2 input duty cycle duty cycle 45 50 55 % lvpecl output duty cycle distortion -5 5 % lvpecl output duty cycle distortion -5 5 % hcsl output duty cycle distortion -5 5 % lvcmos output duty cycle distortion @ 2.5v and 3.3v -5 5 % lvcmos output duty cycle distortion @ 1.8 v, f <100mhz -5 5 % lvcmos output duty cycle distortion @ 1.8 v, f >=100mhz -10 10 % slew rate, slew[1:0] = 11 single-ended 3.3v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 1.7 2.7 4.1 v/ns slew rate, slew[1:0] = 10 single-ended 3.3v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 1.4 2.4 3.8 v/ns slew rate, slew[1:0] = 01 single-ended 3.3v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 1.3 2.3 3.7 v/ns slew rate, slew[1:0] = 00 single-ended 3.3v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 1.1 2.1 3.6 v/ns slew rate, slew[1:0] = 11 single-ended 2.5v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.9 1.7 2.6 v/ns slew rate, slew[1:0] = 10 single-ended 2.5v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.6 1.4 2.3 v/ns slew rate, slew[1:0] = 01 single-ended 2.5v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.6 1.3 2.2 v/ns slew rate, slew[1:0] = 00 single-ended 2.5v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.6 1.2 2.1 v/ns slew rate, slew[1:0] = 11 single-ended 1.8v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.7 1.2 2.1 v/ns slew rate, slew[1:0] = 10 single-ended 1.8v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.4 0.9 1.7 v/ns slew rate, slew[1:0] = 01 single-ended 1.8v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.4 0.8 1.6 v/ns slew rate, slew[1:0] = 00 single-ended 1.8v lvcmos output clock rise and fall time, @ 125mhz 25% to 75% of vddo (output load = 5 pf) 0.3 0.7 1.4 v/ns rise times lvds, 20% to 80%, single-ended 300 fall times lvds, 80% to 20%, single-ended 300 rise times lvpecl, 20% to 80%, single-ended 400 fall times lvpecl, 80% to 20%, single-ended 400 t6 buffer additive phase jitter, rm s fref=125mhz, lvcmos, vpp=1v, integration range: 12khz?20mhz 0.2 ps t7 output skew skew between the same frequencies, with outputs using the same driver format and phase delay set to 0 ns. 35 ps input to output skew skew from input to output 3ns t4 t5 ps fin input frequency fout mhz output frequency t3 output duty cycle distortion
programmable fanout buffer 16 revision d 07/13/15 5P1103 datasheet test circuits and loads test circuits and loads for outputs outx v dda clk out gnd c l 0.1f v ddox 0.1f v ddd 0.1f 33 hcsl output 33 50 50 hcsl differential output test load 2pf 2pf zo=100ohm differential
revision d 07/13/15 17 programmable fanout buffer 5P1103 datasheet 5P1103 application schematic the following figure shows an example of 5P1103 application schematic. input and output terminations shown are intended as examples only and may not represent the exact user configuration. in this example, the device is operated at v ddd, v dda = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. a 12pf parallel resonant 8mhz to 40mhz crystal is used in this example. different crystal frequencies may be used. the c1 = c2 = 5pf are recommended for frequency accuracy. if different crystal types are used, please consult idt for recommendations. for different board layout, the c1 and c 2 may be slightly adjusted for optimizing frequency accuracy. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. 5P1103 provides separate power supplies to isolate any high switching noise from coupling into the part. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if spac e is limited, the 0.1uf capacitor in each power pin filter shoul d be placed on the device side. the other components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of no ise frequencies. this low-pass filter starts to attenuate noi se at approximately 10 khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.
programmable fanout buffer 18 revision d 07/13/15 5P1103 datasheet 5P1103 reference schematic 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a layout notes: 1. separate xout and xin traces by 3 x the trace width 2. do not share crystal load capacitor ground via with other components. 3. route power from bead through bulk capacitor pad then through 0.1uf capacitor pad then to clock chip vdd pad. 4. do not share ground vias. one ground pin one ground via. revision history 0.1 3/05/2015 first publication manufacture part number z@100mhz pkgsz dc res. current(ma) fair-rite 2504021217y0 120 0402 0.5 200 murata blm15ag221sn1 220 0402 0.35 300 murata blm15bb121sn1 120 0402 0.35 300 tdk mmz1005s241a 240 0402 0.18 200 tecstar tb4532153121 120 0402 0.3 300 note:ferrite bead fb1 = place near i2c controller if used lvds termination 3.3v lvpecl termination 2.5v and 3.3v hcsl termination configur ation pull-up for hardware control remove for i2c lvcmos termination for lvds, lvpecl ac couple use termination on right pull-down resistors: 6,7,8,9 and 24 have weak internal the following pins see datasheet for bias network fg_x1 v1p8vca out_0_sel-i2c v1p8vc outr0 clkin clkinb v1p8vc outr1 outrb1 sda v1p8vc scl outr2 outrb2 sd/oe v1p8vc v1p8vc sda scl clkin clkinb out_0_sel-i2c v1p8vca outr2 out_2 fg_x2 v1p8vc v1p8vca vcc1p8 v3p3 v1p8vc size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 05, 2015 5P1103_sch san jose, ca size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 05, 2015 5P1103_sch san jose, ca size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 05, 2015 5P1103_sch san jose, ca c2 1uf 1 2 u3 receiver 1 2 c12 .1uf 1 2 r14 33 1 2 r12 50 1 2 r11 50 1 2 r5 49.9 1% 1 2 c5 .1uf 1 2 c3 .1uf 1 2 c4 .1uf 1 2 u4 receiver 1 2 r15 33 1 2 fb1 signal_bead 1 2 c13 .1uf 1 2 c6 np 1 2 r13 33 1 2 c1 10uf 1 2 r10 50 1 2 r4 49.9 1% 1 2 r9 10k 1 2 r3 100 1 2 gnd gnd y1 25.000 mhz cl = 8pf 4 1 2 3 u2 receiver 1 2 c8 .1uf 1 2 r6 33 1 2 u5 5P1103a xout 3 xin/ref 4 clkin 1 clkinb 2 clksel 6 sel1/sda 8 sel0/scl 9 sd/oe 7 vdda 5 vddd 22 vddo0 23 out0_sel_i2cb 24 vddo1 21 out1 20 out1b 19 vddo2 18 out2 17 out2b 16 vdda 15 nc 14 nc 13 vdda 10 nc 11 nc 12 epad 25 epad 26 epad 27 epad 28 epad 29 epad 30 epad 31 epad 32 epad 33 c7 np 1 2 r2 2.2 1 2 r7 10k 1 2 r8 10k 1 2 idt 603-25-150 25.000mhz cl=8pf
revision d 07/13/15 19 programmable fanout buffer 5P1103 datasheet overdriving the xin/ref interface lvcmos driver the xin/ref input can be overdr iven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xout pin can be left floating. the amplitude of the input signal should be between 500mv and 1.2v and the slew rate should not be less than 0.2v/ns. figure general diagram for lvcmos driver to xtal input interface shows an example of the interface diagram for a lvcmos driver. this configuration has three properties; the total output impedance of ro and rs matches the 50 ohm transmission line impedance, the vrx voltage is generated at the clkin inputs which maintains the lv cmos driver voltage level across the transmission line for best s/n and the r1-r2 voltage divider values ensure that the clock level at xin is less than the maximum value of 1.2v. general diagram for lvcmos driver to xtal input interface table 21 nominal voltage divider va lues vs lvcmos vdd for xin shows resistor values that ensure the maximum drive level for the xin/ref port is no t exceeded for all combinations of 5% tolerance on the driver vdd, the vdda and 5% resistor tolerances. the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the voltage divider attenuation as long as the minimum drive level is maintain ed over all tolerances. to assist this assessment, the total load on the driver is included in the table. table 21:nominal voltage divider values vs lvcmos vdd for xin ? xout xin / ref r1 r2 c3 0. 1 uf v_ xin lv cmos vdd ro ro + rs = 50 o hms rs zo = 50 ohm lvcmos driver vdd ro+rs r1 r2 v_xin (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242
programmable fanout buffer 20 revision d 07/13/15 5P1103 datasheet lvpecl driver figure general diagram for lv pecl driver to xtal input interface shows an example of the interface diagram for a +3.3v lvpecl driver. this is a standard lvpecl termination with one side of the driver f eeding the xin/ref input. it is recommended that all components in the schematics be placed in the layout; though some components might not be used, they can be utilized fo r debugging pu rposes. the datasheet specifications are c haracterized and guaranteed by using a quartz crystal as the input. if the driver is 2.5v lvpecl, the only change necessary is to use the appropriate value of r3. general diagram for +3.3v lvpecl driver to xtal input interface clkin equivalent schematic figure clkin equivalent schematic below shows the basis of the requirements on vih max, vil min and the 1200 mv p-p single ended vswing maximum. ? the clkin and clkinb vih max spec comes from the cathode voltage on the input esd diodes d2 and d4, which are referenced to the intern al 1.2v supply. clkin or clkinb voltages greater th an 1.2v + 0.5v =1.7v will be clamped by these diodes. clkin and clkinb input voltages less than -0.3v will be clamped by diodes d1 and d3. ? the 1.2v p-p maximum vswing input requirement is determined by the internally regulated 1.2v supply for the actual clock receiver. this is th e basis of the vswing spec in table 13. ? +3 .3 v lv pe cl dr iv er zo = 50 ohm zo = 50 ohm r1 50 r2 50 r3 50 xout xin / ref c1 0. 1 uf
revision d 07/13/15 21 programmable fanout buffer 5P1103 datasheet clkin equivalent schematic wiring the differential input to accept single-ended levels figure recommended schematic for wiring a differential input to accept single-ended levels shows how a differential input can be wired to accept single ended levels. this configuration has three properties; the total output impedance of ro and rs matches the 50 ohm transmission line impedance, the vrx voltage is generated at the clkin inputs which maintains the lvcmos driv er voltage level across the transmission line fo r best s/n and the r1-r2 voltage divider values ensure that vrx p-p at clkin is less than the maximum value of 1.2v. recommended schematic for wiring a differential input to accept single-ended levels ? r1 r2 vrx versaclock 5 receiver clki n clki nb lv cmos vdd zo = 50 ohm ro + rs = 5 0 rs ro
programmable fanout buffer 22 revision d 07/13/15 5P1103 datasheet table 22 nominal voltage divider values vs driver vdd shows resistor values that ensu re the maximum drive level for the clkin port is not exceeded for all combinations of 5% tolerance on the driver vdd, the vddo_0 and 5% resistor tolerances. the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the impedance of the r1-r2 divider. to assist this assessment, the total load on th e driver is in cluded in the table. table 22:nominal voltage divi der values vs driver vdd hcsl differential clock input interface clkin/clkinb will accept dc coupled hcsl signals. clkin, clkinb input driven by an hcsl driver 3.3v differential lvpecl clock input interface the logic levels of 3.3v l vpecl and lvds can exceed vih max for the clkin/b pins. theref ore the lvpecl levels must be ac coupled to the differential input and the dc bias restored with external voltage dividers. a single table of bias resistor values is provided below for both for 3.3v lvpecl and lvds. vbias can be vddd, v ddox or any other available voltage at the receiver that is most conveniently accessible in layout. clkin, clkinb input driven by a 3.3v lvpecl driver lvcmos driver vdd ro+rs r1 r2 vrx (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242 zo=50ohm zo=50ohm clkin clkinb receiver q nq +3.3v lvpecl driver zo=50ohm zo=50ohm receiver r9 r10 50ohm 50ohm vbias rpu1 rpu2 clkin clkinb rtt 50ohm c5 0.01f c6 0.01f r15 4.7kohm r13 4.7kohm
revision d 07/13/15 23 programmable fanout buffer 5P1103 datasheet clkin, clkinb input driven by an lvds driver table 23:bias resistors for 3.3v lv pecl and lvds drive to clkin/b 2.5v differential lvpecl clock input interface the maximum dc 2.5v lvpecl voltage meets the vih max clkin requirement. therefore 2.5v lvpecl can be connected directly to the clki n terminals with out ac coupling clkin, clkinb input driven by a 2.5v lvpecl driver lvds driver zo=50ohm zo=50ohm receiver rterm 100ohm vbias rpu1 rpu2 clkin clkinb c1 0.1f c2 0.1f r1 4.7kohm r2 4.7kohm vbias (v) rpu1/2 (kohm) clkin/b bias voltage (v) 3.3 22 0.58 2.5 15 0.60 1.8 10 0.58 +2.5v lvpecl driver zo=50ohm zo=50ohm r1 r2 50ohm 50ohm rtt 18ohm receiver clkin clkinb
programmable fanout buffer 24 revision d 07/13/15 5P1103 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? . and 132 ? . the actual value should be select ed to match the differential impedance (zo) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? . differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the rece iver as possible. the standard termination schematic as shown in figure standard termination or the termination of figure optional termination can be used, which uses a center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. in addition , since these outputs are lvds compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the idt lvds output. if using a non-standard termination, it is recommended to contact idt and confirm that the termination will function as in tended. for ex ample, the lvds outputs cannot be ac coupled by placing capacitors between the lvds outputs and the 100 ohm shunt load. if ac coupling is required, the coupling caps must be placed between the 100 ohm shunt termination and the receiver. in this manner the termination of the lvds output remains dc coupled lvds driver lvds driver lvds receiver lvds receiver z t c z o ? z t z o ? z t z t 2 z t 2 standard termination optional termination
revision d 07/13/15 25 programmable fanout buffer 5P1103 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two di fferent layouts mentioned are recommended only as guidelines. the differential outputs gener ate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. the figure below show two different layouts which are recommended only as guidelines. other suitab le clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3v lvpecl output termination (1) 3.3v lvpecl output termination (2) lvpecl zo=50ohm zo=50ohm 3.3v r1 r2 3.3v 50ohm 50ohm rtt 50ohm input + - lvpecl zo=50ohm zo=50ohm 3.3v + - input r1 r2 3.3v 84ohm 84ohm 3.3v r3 r4 125ohm 125ohm
programmable fanout buffer 26 revision d 07/13/15 5P1103 datasheet termination for 2.5v lvpecl outputs figures 2.5v lvpecl driver termin ation example (1) and (2) show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v ddo ? 2v. for v ddo = 2.5v, the v ddo ? 2v is very close to ground level. the r3 in figure 2.5v lvpecl driver termination example (3) can be eliminated and the termination is shown in example (2). 2.5v lvpecl driver termination example (1) 2.5v lvpecl driver termination example (2) 2.5v lvpecl driver termination example (3) 2.5v lvpecl driver zo=50ohm zo=50ohm 2.5v + - r2 r4 v ddo = 2.5v 62.5ohm 62.5ohm 2.5v r1 r3 250ohm 250ohm 2.5v lvpecl driver zo=50ohm zo=50ohm 2.5v + - r1 r2 v ddo = 2.5v 50ohm 50ohm 2.5v lvpecl driver zo=50ohm zo=50ohm 2.5v + - r1 r2 v ddo = 2.5v 50ohm 50ohm r3 18ohm
revision d 07/13/15 27 programmable fanout buffer 5P1103 datasheet pci express application note pci express jitter analysis me thodology models the system response to reference clock jit ter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the ji tter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respec tively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer fu nction to the clock spectrum x(s) and is: in order to generate time doma in jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen1 magnitude of transfer function for pci express gen2, two transfe r functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen2a magnitude of transfer function pcie gen2b magnitude of transfer function for pci express gen 3, one transfer function is defined and the evaluation is performed ov er the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
programmable fanout buffer 28 revision d 07/13/15 5P1103 datasheet pcie gen3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference cl ock requirements. marking diagram 1. line 1 is the truncated part number. 2. ?ddd? denotes dash code. 3. ?yww? is the last digit of the year and week that the part was assembled. 4. ? ** ? denotes sequential lot number. 5. ?$? denotes mark code. 1103a ddd yww**$
revision d 07/13/15 29 programmable fanout buffer 5P1103 datasheet package outline and package dimensions (24-pin 4mm x 4mm vfqfpn) www.idt.com t i d
programmable fanout buffer 30 revision d 07/13/15 5P1103 datasheet package outline and pack age dimensions, cont. (24-pin 4mm x 4mm vfqfpn) www.idt.com t i d
revision d 07/13/15 31 programmable fanout buffer 5P1103 datasheet ordering information note: ?ddd? denotes specific order codes. ?g? after the two-letter package code denotes pb-free configuration, rohs compliant. revision history part / order number marking shipping packaging package temperature 5P1103adddnlgi see page 29 trays 24-pin vfqfpn -40 to +85c 5P1103adddnlgi8 tape and reel 24-pin vfqfpn -40 to +85c rev. date originator description of change a 04/15/15 b. chandhoke initial release. b 04/30/15 b. chandhoke replaced ?clock buffer? with ?fanout buffer? removed ?a? version letter from part number title header c 06/19/15 b. chandhoke removed the ?output divides? section. d 07/13/15 b. chandhoke 1. added conditions text and min/max values for vih/vil. 2. updated 1.8v, 2.5v, and 3.3v vih/vil conditions text and min/max values for "single-ended inputs - clksel, sd/oe" 3. added idt and fox crystal references.
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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